HD6413002 Datasheet, PDF (204/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.
Channel A
Bit 2 Bit 1 Bit 0
DTS2A DTS1A DTS0A Description
0
0
0
Compare match/input capture A interrupt from ITU (Initial value)
channel 0
1
Compare match/input capture A interrupt from ITU channel 1
1
0
Compare match/input capture A interrupt from ITU channel 2
1
Compare match/input capture A interrupt from ITU channel 3
1
0
0
Transmit-data-empty interrupt from SCI channel 0
1
Receive-data-full interrupt from SCI channel 0
1
—*
Transfer in full address mode
Note: * See section 8.3.4, Data Transfer Control Register (DTCR).
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