HD6413002 Datasheet, PDF (381/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T₃ state of a general register read cycle, the value before input capture is read.
See figure 10-66.
General register read cycle
T₁
T₂
T₃
ø
Address
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 10-66 Contention between General Register Read and Input Capture
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