HD6413002 Datasheet, PDF (163/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

7.3 Operation
7.3.1 Area Division
One of three functions can be selected for the H8/3002 refresh controller: interfacing to
DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval
timing. Table 7-3 summarizes the register settings when these three functions are used.
Table 7-3 Refresh Controller Settings
Register Settings
RFSHCR SRFMD
PSRAME
DRAME
CAS/WE
M9/M8
RTCOR
RTMCSR
RFSHE
RCYCE
CKS2 to CKS0
CMF
CMIE
P8DDR
ABWCR
P8₁DDR
ABW3
Usage
DRAM Interface
PSRAM Interface
Selects self-refresh mode
Cleared to 0
Set to 1
Set to 1
Cleared to 0
Selects 2CAS or
—
2WE mode
Selects column
—
addressing mode
Selects RFSH signal output
Selects insertion of refresh cycles
Refresh interval setting
Set to 1 when RTCNT = RTCOR
Cleared to 0
Set to 1 (CS₃ output)
Cleared to 0
—
Interval Timer
Cleared to 0
Cleared to 0
Cleared to 0
—
—
Cleared to 0
—
Interrupt interval setting
Enables or disables
interrupt requests
Set to 0 or 1
—
DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR,
RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1.
Set bit P8₁DDR to 1 in the port 8 data direction register (P8DDR) to enable CS₃ output. In
ABWCR, make area 3 a 16-bit-access area.
Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize
RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit
DRAME to 0. Set bit P8₁DDR to 1 in P8DDR to enable CS₃ output.
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