HD6413002 Datasheet, PDF (561/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

18.3.3 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 18-15 shows the reset input timing.
• Reset output timing
Figure 18-16 shows the reset output timing.
• Interrupt input timing
Figure 18-17 shows the input timing for NMI and IRQ₅ to IRQ₀.
• Bus-release mode timing
Figure 18-18 shows the bus-release mode timing.
ø
RES
t_RESS
t_RESS
t_RESW
Figure 18-15 Reset Input Timing
ø
RESO
t_RESD
t_RESD
t_RESOW
Figure 18-16 Reset Output Timing
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