HD6413002 Datasheet, PDF (371/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture
A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU
output. Figure 10-55 shows the timing.
ø
TIOCA₁ pin
Input capture
signal
TOER
N
ITU output
pins
ITU output
ITU output
N: Arbitrary setting (H'C1 to H'FF)
H'C0
N
H'C0
I/O port
Generic
input/output
ITU output
ITU output
I/O port
Generic
input/output
Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example)
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10-56 shows the timing.
T₁
T₂
T₃
ø
Address
TOCR address
TOCR
ITU output pin
Inverted
Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
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