HD6413002 Datasheet, PDF (552/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

18.3 Operational Timing
This section shows timing diagrams.
18.3.1 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 18-4 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 18-5 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 18-6 shows the timing of the external three-state access cycle with one wait state
inserted.
540