HD6413002 Datasheet, PDF (154/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Section 7 Refresh Controller
7.1 Overview
The H8/3002 has an on-chip refresh controller that enables direct connection of 16-bit-wide
DRAM or pseudo-static RAM (PSRAM).
DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space.
A maximum 128 kbytes can be connected in modes 1 and 2 (1-Mbyte modes). A maximum
2 Mbytes can be connected in modes 3 and 4 (16-Mbyte modes).
Systems that do not need to refresh DRAM or pseudo-static RAM can use the refresh controller as
an 8-bit interval timer.
7.1.1 Features
The refresh controller can be used for one of three functions: DRAM refresh control, pseudo-static
RAM refresh control, or interval timing. Features of the refresh controller are listed below.
Features as a DRAM Refresh Controller
• Enables direct connection of 16-bit-wide DRAM
• Selection of 2CAS or 2WE mode
• Selection of 8-bit or 9-bit column address multiplexing for DRAM address input
Examples:
— 1-Mbit DRAM: 8-bit row address × 8-bit column address
— 4-Mbit DRAM: 9-bit row address × 9-bit column address
— 4-Mbit DRAM: 10-bit row address × 8-bit column address
• CAS-before-RAS refresh control
• Software-selectable refresh interval
• Software-selectable self-refresh mode
• Wait states can be inserted
Features as a Pseudo-Static RAM Refresh Controller
• RFSH signal output for refresh control
• Software-selectable refresh interval
• Software-selectable self-refresh mode
• Wait states can be inserted
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