HD6413002 Datasheet, PDF (224/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, and external request
signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8-7 shows a sample setup procedure for repeat mode.
Repeat mode
1. Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
Set source and
destination addresses
1
2. Set the transfer count in both ETCRH and ETCRL.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
Set transfer count
2
• Clear the DTIE bit to 0 and set the RPE bit to 1
to select repeat mode.
• Select MAR increment or decrement with the DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Read DTCR
3
Set DTCR
4
Repeat mode
Figure 8-7 Repeat Mode Setup Procedure (Example)
210