HD6413002 Datasheet, PDF (248/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

8.5 Interrupts
The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.
Table 8-13 DMAC Interrupts
Interrupt
DEND0A
DEND0B
DEND1A
DEND1B
Description
Short Address Mode
Full Address Mode
End of transfer on channel 0A
End of transfer on
channel 0
End of transfer on channel 0B
—
End of transfer on channel 1A
End of transfer on
channel 1
End of transfer on channel 1B
—
Interrupt Priority
High
Low
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.
Figure 8-25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
DTE
DTIE
DMA-end interrupt
Figure 8-25 DMA-End Interrupt Logic
The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The
DTME bit does not affect interrupt operations.
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