HD6413002 Datasheet, PDF (12/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Section 12 Watchdog Timer ........................................................................................ 403
12.1 Overview ........................................................................................................................ 403
12.1.1 Features........................................................................................................... 403
12.1.2 Block Diagram................................................................................................ 404
12.1.3 Pin Configuration............................................................................................ 404
12.1.4 Register Configuration.................................................................................... 405
12.2 Register Descriptions...................................................................................................... 406
12.2.1 Timer Counter (TCNT)................................................................................... 406
12.2.2 Timer Control/Status Register (TCSR)........................................................... 407
12.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 409
12.2.4 Notes on Register Access ............................................................................... 411
12.3 Operation ........................................................................................................................ 413
12.3.1 Watchdog Timer Operation............................................................................. 413
12.3.2 Interval Timer Operation ................................................................................ 414
12.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 415
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 416
12.4 Interrupts ........................................................................................................................ 417
12.5 Usage Notes .................................................................................................................... 417
Section 13 Serial Communication Interface........................................................... 419
13.1 Overview ........................................................................................................................ 419
13.1.1 Features........................................................................................................... 419
13.1.2 Block Diagram................................................................................................ 421
13.1.3 Input/Output Pins............................................................................................ 422
13.1.4 Register Configuration.................................................................................... 422
13.2 Register Descriptions...................................................................................................... 423
13.2.1 Receive Shift Register (RSR) ......................................................................... 423
13.2.2 Receive Data Register (RDR)......................................................................... 423
13.2.3 Transmit Shift Register (TSR)........................................................................ 424
13.2.4 Transmit Data Register (TDR) ....................................................................... 424
13.2.5 Serial Mode Register (SMR) .......................................................................... 425
13.2.6 Serial Control Register (SCR) ........................................................................ 429
13.2.7 Serial Status Register (SSR) ........................................................................... 433
13.2.8 Bit Rate Register (BRR) ................................................................................. 437
13.3 Operation ........................................................................................................................ 446
13.3.1 Overview......................................................................................................... 446
13.3.2 Operation in Asynchronous Mode.................................................................. 448
13.3.3 Multiprocessor Communication ..................................................................... 457
13.3.4 Synchronous Operation .................................................................................. 464
13.4 SCI Interrupts.................................................................................................................. 473
13.5 Usage Notes .................................................................................................................... 474