HD6413002 Datasheet, PDF (547/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Table 18-5 Refresh Controller Bus Timing
Condition A:
Condition B:
Condition C:
Condition D:
V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 8 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_REF = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 8 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AVCC ,
V_SS = AV_SS = 0 V, ø = 2 MHz to 16 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 17 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C Condition D
Item
8 MHz
10 MHz
16 MHz
17MHz
Test
Symbol Min Max Min Max Min Max Min Max Unit Conditions
RAS delay time 1
RAS delay time 2
RAS delay time 3
t_RAD1 — 60 — 50 —
30
— 30 ns Figure 18-7
t_RAD2 — 60 — 50 —
30
— 30
to
Figure 18-13
t_RAD3 — 60 — 50 —
30
— 30
Row address hold time* t_RAH 25 — 20 — 15
RAS precharge time* t_RP
85 — 70 — 40
CAS to RAS precharge t_CRP 85 — 70 — 40
time*
— 16.4 —
— 42.8 —
— 42.8 —
CAS pulse width
RAS access time*
t_CAS 110 — 85 — 40
—
35 —
t_RAC — 160 — 150 —
85
— 76.6
Address access time t_AA
— 105 — 75 —
55
— 45
CAS access time
t_CAC — 50 — 50 —
25
— 27.8
Write data setup time 3 t_WDS3 75 — 50 — 40
CAS setup time*
t_CSR 20 — 15 — 15
— 10 —
— 11.4 —
Read strobe delay time t_RSD — 60 — 50 —
30
— 30
Note: *At 8 MHz (condition A), the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 38 (ns) t_CAC = 1.0 × t_CYC – 75 (ns)
t_RAC = 2.0 × t_CYC – 90 (ns)
t_CSR = 0.5 × t_CYC – 43 (ns) t_RP = t_CRP = 1.0 × t_CYC – 40 (ns)
At 10 MHz (condition B), the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 30 (ns) t_CAC = 1.0 × t_CYC – 50 (ns)
t_RAC = 2.0 × t_CYC – 50 (ns)
t_CSR = 0.5 × t_CYC – 35 (ns) t_RP = t_CRP = 1.0 × t_CYC – 30 (ns)
At 16 MHz (condition C), the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 16 (ns) t_CAC = 1.0 × t_CYC – 38 (ns)
t_RAC = 2.0 × t_CYC – 40 (ns)
t_CSR = 0.5 × t_CYC – 16 (ns) t_RP = t_CRP = 1.0 × t_CYC – 23 (ns)
At 17 MHz (condition D), the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 13 (ns) t_CAC = 1.0 × t_CYC – 31 (ns)
t_RAC = 2.0 × t_CYC – 41 (ns)
t_CSR = 0.5 × t_CYC – 18 (ns) t_RP = t_CRP = 1.0 × t_CYC – 16 (ns)
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