HD6413002 Datasheet, PDF (528/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

17.3 Sleep Mode
17.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the
SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA
controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode.
17.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked in the CPU.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
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