HD6413002 Datasheet, PDF (549/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Table 18-7 Timing of On-Chip Supporting Modules
Condition A:
Condition B:
Condition C:
Condition D:
V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 8 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_REF = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 10 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 16 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 17 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C Condition D
Item
8 MHz
10 MHz
16 MHz
17 MHz
Test
Symbol Min Max Min Max Min Max Min Max Unit Conditions
DMAC DREQ setup t_DRQS 40 — 40 — 30
—
30
– ns Figure 18-27
time
DREQ hold
t_DRQH 10 — 10 — 10
—
10
–
time
TEND delay t_TED1 — 100 — 100 —
50
–
50
time 1
Figure 18-25,
Figure 18-26
TEND delay t_TED2 — 100 — 100 —
50
–
50
time 2
ITU Timer output t_TOCD — 100 — 100 — 100 – 100 ns Figure 18-21
delay time
Timer input
t_TICS 50 — 50 — 50
—
50
–
setup time
Timer clock
t_TCKS 50 — 50 — 50
—
50
–
input setup time
Figure 18-22
Timer Single t_TCKWH 1.5 — 1.5 — 1.5
—
1.5
– t_CYC
clock edge t_TCKWL
pulse _Both
width _edges
2.5 — 2.5 — 2.5 — 2.5 –
SCI Input Asyn- t_SCYC 4
—
4
—
4
—
4
–
clock chronous
cycle _Syn-
t_SCYC 6
—
6
—
6
—
6
–
chronous
Figure 18-23
Input clock rise t_SCKr — 1.5 — 1.5 —
1.5
–
1.5
time
Input clock fall t_SCKf — 1.5 — 1.5 —
1.5
–
1.5
time
Input clock
pulse width
t_SCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t_SCYC
537