HD6413002 Datasheet, PDF (692/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Appendix D Pin States
D.1 Port States in Each Mode
Table D-1 Port States
Pin
Name
Mode
Reset
State
Hardware Software
Standby Standby
Mode Mode
Bus-
Released
Mode
Program
Execution
Sleep Mode
ø
—
Clock output T
H
Clock output Clock output
RESO
—
T*²
T
T
T
RESO
A₁₉ to A₀
D₁₅ to D₈
AS, RD,
HWR, LWR
1 to 4
1 to 4
1 to 4
L
T
T
T
A₁₉ to A₀
T
T
T
T
D₁₅ to D₀
H
T
T
T
AS, RD,
HWR, LWR
P4₇ to P4₀
D₇ to D₀
P6₀
1 to 4 8-bit bus T
16-bit bus
1 to 4
T
T
keep
keep
I/O port
T
T
D₇ to D₀
T
keep
keep
I/O port*¹
WAIT
P6₁
1 to 4
T
T
(BRLE = 0) T
I/O port
keep
BREQ
(BRLE = 1)
T
P6₂
1 to 4
T
T
(BRLE = 0)
I/O port
keep
L
(BRLE = 0)
(BRLE = 1)
or BACK
H
(BRLE = 1)
P7₇ to P7₀ 1 to 4
T
T
T
T
Input port
Note: *¹ Do not set the DDR bit to 1.
*² Low output only when WDT overflow causes a reset.
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
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