HD6413002 Datasheet, PDF (374/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

ø
TCNT
Overflow
signal
OVF
H'FFFF
H'0000
OVI
Figure 10-59 Timing of Setting of OVF
10.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10-60 shows the timing.
TSR write cycle
T₁
T₂
T₃
ø
Address
TSR address
IMF, OVF
Figure 10-60 Timing of Clearing of Status Flags
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