HD6413002 Datasheet, PDF (8/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.4.1
6.4.2
6.4.3
Connection to Dynamic RAM and Pseudo-Static RAM ................................ 135
Register Write Timing .................................................................................... 135
BREQ Input Timing........................................................................................ 137
Section 7 Refresh Controller .................................................................................... 139
7.1 Overview ........................................................................................................................ 139
7.1.1 Features........................................................................................................... 139
7.1.2 Block Diagram................................................................................................ 140
7.1.3 Input/Output Pins............................................................................................ 141
7.1.4 Register Configuration.................................................................................... 141
7.2 Register Descriptions...................................................................................................... 142
7.2.1 Refresh Control Register (RFSHCR) ............................................................. 142
7.2.2 Refresh Timer Control/Status Register (RTMCSR) ....................................... 145
7.2.3 Refresh Timer Counter (RTCNT)................................................................... 147
7.2.4 Refresh Time Constant Register (RTCOR) .................................................... 147
7.3 Operation ........................................................................................................................ 148
7.3.1 Area Division.................................................................................................. 148
7.3.2 DRAM Refresh Control.................................................................................. 149
7.3.3 Pseudo-Static RAM Refresh Control.............................................................. 164
7.3.4 Interval Timing ............................................................................................... 169
7.4 Interrupt Source .............................................................................................................. 175
7.5 Usage Notes .................................................................................................................... 175
Section 8 DMA Controller ........................................................................................ 179
8.1 Overview ........................................................................................................................ 179
8.1.1 Features........................................................................................................... 179
8.1.2 Block Diagram................................................................................................ 180
8.1.3 Functional Overview ...................................................................................... 181
8.1.4 Input/Output Pins............................................................................................ 182
8.1.5 Register Configuration.................................................................................... 182
8.2 Register Descriptions (1) (Short Address Mode) ........................................................... 184
8.2.1 Memory Address Registers (MAR)................................................................ 185
8.2.2 I/O Address Registers (IOAR)........................................................................ 186
8.2.3 Execute Transfer Count Registers (ETCR) .................................................... 186
8.2.4 Data Transfer Control Registers (DTCR) ....................................................... 188
8.3 Register Descriptions (2) (Full Address Mode).............................................................. 192
8.3.1 Memory Address Registers (MAR)................................................................ 192
8.3.2 I/O Address Registers (IOAR)........................................................................ 192
8.3.3 Execute Transfer Count Registers (ETCR) .................................................... 193
8.3.4 Data Transfer Control Registers (DTCR) ....................................................... 195
8.4 Operation ........................................................................................................................ 201