HD6413002 Datasheet, PDF (131/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.3.4 Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper address bus (D₁₅ to D₈) is used to access these areas. The LWR
pin is always high. Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
ø
Address bus
CS _n
AS
External address in area n
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
High
D₇ to D ₀
Note: n = 7 to 0 (but for CS_n, n = 3 to 0)
Valid
Undetermined data
Figure 6-4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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