HD6413002 Datasheet, PDF (218/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Address T
Transfer
1 byte or word is
transferred per request
IOAR
Address B
Legend
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (–1) ^DTID • (2 ^DTSZ • N – 1)
Figure 8-2 Operation in I/O Mode
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCR to H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, SCI channel 0 transmit-data-empty and receive-data-full interrupts, and external
request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
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