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| HD6413002 Datasheet, PDF (558/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller | |||
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ø
A9 to A1
AS
T1
tAD
CS3 (RAS)
tAS1
HWR (UCAS),
LWR (LCAS)
RD (WE)
(read)
RD (WE)
(write)
RFSH
D15 to D0
(read)
D15 to D0
(write)
T2
T3
tAD
tRtRAAHD1
tASD
tAS1
tRAD3
tCAS
tSD
tRP
tCRP
tASD
tRAC
tAA
tCAC
tSD
tWDH
tWDS3
tRDS
tRDH *
Note: * Stipulation from earliest CS3 and RD negate timing.
Figure 18-10 DRAM Bus Timing (Read/Write): Three-State Access
â 2CAS Mode â
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