HD6413002 Datasheet, PDF (220/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Table 8-7 Register Functions in Idle Mode
Register
23
0
MAR
23
All 1s
7
0
IOAR
15
0
ETCR
Function
Activated by
SCI Receive-
Data-Full
Interrupt
Other
Activation
Initial Setting
Destination
address
register
Source
address
register
Destination or
source address
Source
address
register
Destination Source or
address destination
register
address
Transfer counter
Number of
transfers
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Operation
Held fixed
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 8-4 illustrates how idle mode operates.
MAR
Transfer
1 byte or word is
transferred per request
Figure 8-4 Operation in Idle Mode
206
IOAR