HD6413002 Datasheet, PDF (149/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Figure 6-19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
ø
Address
bus
Data bus
(D₁₅ to D₀ )
AS , RD High
HWR , LWR
CPU cycles
T₁
T₂
Address
External bus released
CPU cycles
High-impedance
High-impedance
High-impedance
High-impedance
BREQ
BACK
Minimum 2 cycles
1
2
3
4
5
6
1 Low BREQ signal is sampled at rise of T₁ state.
2 BACK signal goes low at end of CPU read cycle, releasing bus right to external bus master.
3 BREQ pin continues to be sampled while bus is released to external bus master.
4, 5 High BREQ signal is sampled twice consecutively.
6 BREQ signal goes high, ending bus-release cycle.
Figure 6-19 Interconnections with Memory (Example)
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