HD6413002 Datasheet, PDF (544/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

18.2.2 AC Characteristics
Bus timing parameters are listed in table 18-4. Refresh controller bus timing parameters are listed
in table 18-5. Control signal timing parameters are listed in table 18-6. Timing parameters of the
on-chip supporting modules are listed in table 18-7.
Table 18-4 Bus Timing (1)
Condition A:
Condition B:
Condition C:
Condition D:
V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 8 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_REF = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 10 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 16 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 17 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C Condition D
Item
8 MHz
10 MHz
16 MHz
17 MHz
Test
Symbol Min Max Min Max Min Max Min Max Unit Conditions
Clock cycle time
t_CYC 125 500 100 500 62.5 500 58.8 500 ns Figure 18-4,
Clock low pulse width t_CL
40
—
30
—
20
—
17
— t_cyc ^{Figure 18-5}
Clock high pulse width t_CH
40 — 30 — 20 — 17 —
Clock rise time
t_CR
— 20 — 15 — 10 — 10 ns
Clock fall time
t_CF
— 20 — 15 — 10 — 10
Address delay time
t_AD
— 60 — 50 — 30 — 25
Address hold time
t_AH
25 — 20 — 10 — 10 —
Address strobe delay t_ASD — 60 — 40 — 30 — 25
time
Write strobe delay time t_WSD — 60 — 50 — 30 — 25
Strobe delay time
t_SD
— 60 — 50 — 30 — 25
Write data strobe pulse t_WSW1* 85 — 60 — 35 — 34.8 —
width 1
Write data strobe pulse t_WSW2* 150 — 110 — 65 — 66.2 —
width 2
Address setup time 1 t_AS1 20 — 15 — 10 — 10 —
Address setup time 2 t_AS2 80 — 65 — 40 — 38 —
Read data setup time t_RDS 50 — 35 — 20 — 15 —
Read data hold time
t_RDH
0
—
0
—
0
—
0
—
532