HD6413002 Datasheet, PDF (309/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
0
1
Description
Channel 0 operates normally
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
10.2.4 Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset-
synchronized PWM mode, and buffering for channels 3 and 4.
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
2
1
0
— CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
1
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Combination mode 1/0
These bits select complementary
PWM mode or reset-synchronized
PWM mode for channels 3 and 4
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
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