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HD6413002 Datasheet, PDF (545/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller
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Table 18-4 Bus Timing (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition D: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 17 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C Condition D
8 MHz
10 MHz
16 MHz
17 MHz
Item
Symbol Min Max Min Max Min Max Min Max
Write data delay time tWDD — 75 — 75 — 60 — 55
Write data setup time 1 tWDS1 60 — 65 — 35 — 10 —
Write data setup time 2 tWDS2 15 — 10 —
5
— -10 —
Write data hold time tWDH 25 — 20 — 20 — 20 —
Read data access
time 1
tACC1* — 110 — 100 — 55 — 54.2
Read data access
time 2
tACC2* — 230 — 200 — 115 — 113
Read data access
time 3
tACC3* — 55 — 50 — 25 — 22.8
Read data access
time 4
tACC4* — 160 — 150 — 85 — 86.6
Precharge time
tPCH* 85 — 60 — 40 — 37.8 —
Wait setup time
tWTS 40 — 40 — 25 — 25 —
Wait hold time
tWTH 10 — 10 —
5
—
5
—
Bus request setup time tBRQS 40 — 40 — 40 — 40 —
Bus acknowledge
delay time 1
tBACD1 — 60 — 50 — 30 — 30
Bus acknowledge
delay time 2
tBACD2 — 60 — 50 — 30 — 30
Bus-floating time
tBZD — 70 — 70 — 40 — 40
Note is on next page.
Test
Unit Conditions
ns Figure 18-4,
Figure 18-5
ns Figure 18-6
ns Figure 18-18
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