HD6413002 Datasheet, PDF (120/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.1.3 Input/Output Pins
Table 6-1 summarizes the bus controller’s input/output pins.
Table 6-1 Bus Controller Pins
Name
Chip select 0 to 3
Address strobe
Read
High write
Low write
Wait
Bus request
Bus acknowledge
Abbreviation I/O
CS₀ to CS₃
AS
Output
Output
RD
Output
HWR
Output
LWR
Output
WAIT
BREQ
BACK
Input
Input
Output
Function
Strobe signals selecting areas 0 to 3
Strobe signal indicating valid address output on the
address bus
Strobe signal indicating reading from the external
address space
Strobe signal indicating writing to the external
address space, with valid data on the upper data
bus (D₁₅ to D₈)
Strobe signal indicating writing to the external
address space, with valid data on the lower data
bus (D₇ to D₀)
Wait request signal for access to external three-
state-access areas
Request signal for releasing the bus to an external
device
Acknowledge signal indicating the bus is released
to an external device
6.1.4 Register Configuration
Table 6-2 summarizes the bus controller’s registers.
Table 6-2 Bus Controller Registers
Address* Name
H'FFEC Bus width control register
H'FFED Access state control register
H'FFEE Wait control register
H'FFEF Wait state controller enable register
H'FFF3 Bus release control register
Note: * Lower 16 bits of the address.
Abbrevi-
ation
R/W
ABWCR R/W
ASTCR R/W
WCR
R/W
WCER R/W
BRCR R/W
Initial Value
Modes 1 & 3 Modes 2 & 4
H'FF
H'00
H'FF
H'FF
H'F3
H'F3
H'FF
H'FF
H'FE
H'FE
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