HD6413002 Datasheet, PDF (129/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.3.2 Chip Select Signals
For each of areas 0 to 3, the H8/3002 can output a chip select signal (CS₀ to CS₃) that goes low to
indicate when the area is selected. Figure 6-3 shows the output timing of a CSn signal (n = 0 to 3).
Output of the CS_n signal is enabled or disabled in the data direction register (DDR) of the
corresponding port. A reset leaves pin CS₀ in the output state and pins CS₁ to CS₃ in the input
state. To output chip select signals CS₁ to CS₃, the corresponding DDR bits must be set to 1.
For details see section 9, I/O Ports.
The CS_n signals are decoded from the address signals. They can be used as chip select signals for
SRAM and other devices.
ø
Address
bus
CS_n
T₁
T₂
T₃
External address in area n
Figure 6-3 CS_n Output Timing (n = 0 to 3)
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