HD6413002 Datasheet, PDF (150/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

6.4 Usage Notes
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM
A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is
connected to area 3. For details see section 7, Refresh Controller.
6.4.2 Register Write Timing
ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER
takes effect starting from the next bus cycle. Figure 6-20 shows the timing when an instruction
fetched from area 0 changes area 0 from three-state access to two-state access.
ø
Address
bus
T₁
T₂
T₃
T₁
T₂
T₃
3-state access to area 0
ASTCR address
T₁
T₂
2-state access
to area 0
Figure 6-20 ASTCR Write Timing
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