HD6413002 Datasheet, PDF (526/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

17.2 Register Configuration
The H8/3002’s system control register (SYSCR) controls the power-down state. Table 17-2
summarizes this register.
Table 17-2 Control Register
Address* Name
H'FFF2
System control register
Note: * Lower 16 bits of the address.
Abbreviation R/W
SYSCR
R/W
Initial Value
H'0B
17.2.1 System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 UE NMIEG — RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control
the power-down state. For information on the other SYSCR bits, see section 3.3, System Control
Register.
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