HD6413002 Datasheet, PDF (222/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

8.4.4 Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat
mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCR are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full
interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 8-8 indicates the register functions in repeat mode.
Table 8-8 Register Functions in Repeat Mode
Register
23
0
MAR
23
All 1s
7
0
IOAR
7
0
ETCRH
7
0
ETCRL
Function
Activated by
SCI Receive-
Data-Full
Interrupt
Other
Activation Initial Setting
Operation
Destination
address
register
Source
address
register
Destination or
source address
Incremented or
decremented at
each transfer until
ETCRH reaches
H'0000, then restored
to initial value
Source
address
register
Destination Source or
address destination
register address
Held fixed
Transfer counter
Number of
transfers
Decremented once
per transfer unti
H'0000 is reached,
then reloaded from
ETCRL
Initial transfer count
Number of
transfers
Held fixed
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
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