HD6413002 Datasheet, PDF (242/700 Pages) Renesas Technology Corp – High-performance single-chip microcontroller

Figure 8-19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
DMAC cycle
(channel 1)
CPU
cycle
DMAC cycle
(channel 0A)
CPU
cycle
DMAC cycle
(channel 1)
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂
ø
Address
bus
RD
HWR ,
LWR
Figure 8-19 Timing of Multiple-Channel Operations in the Same Group
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