M1A3P1000-1PQ208M Datasheet, PDF (9/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based military ProASIC3/EL devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The military ProASIC3/EL family device architecture mitigates the need
for ASIC migration at higher volumes. This makes the military ProASIC3/EL family a cost-effective ASIC
replacement.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of military ProASIC3/EL
flash-based FPGAs. Once it is programmed, the flash cell configuration element of military ProASIC3/EL
FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or
soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using
error detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The military ProASIC3/EL family offers many benefits, including nonvolatility and reprogrammability,
through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS
design techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary military ProASIC3/EL architecture provides granularity comparable to standard-cell
ASICs. The military ProASIC3/EL device consists of five distinct and programmable architectural
features (Figure 1-1 on page 1-4 and Figure 1-2):
• FPGA VersaTiles
• Dedicated FlashROM
• Dedicated SRAM/FIFO memory
• Extensive CCCs and PLLs
• I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the military ProASIC3/EL core tile, as either a three-input lookup table
(LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The
VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
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