M1A3P1000-1PQ208M Datasheet, PDF (26/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only
VMV (V)
Static Power
PDC6 (mW)¹
Dynamic Power
PAC9 (µW/MHz)²
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.22
3.3 V LVCMOS – Wide Range
3.3
–
16.22
2.5 V LVCMOS
2.5
–
4.65
1.8 V LVCMOS
1.8
–
1.65
1.5 V LVCMOS (JESD8-11)
1.5
–
0.98
3.3 V PCI
3.3
–
17.64
3.3 V PCI-X
3.3
–
17.64
Differential
LVDS
2.5
2.26
0.83
LVPECL
3.3
5.72
1.81
Notes:
1. PDC6 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VMV.
Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only
VMV (V)
Static Power
PDC6 (mW) ¹
Dynamic Power
PAC9 (µW/MHz) ²
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.23
3.3 V LVCMOS – Wide Range
3.3
–
16.23
2.5 V LVCMOS
2.5
–
4.66
1.8 V LVCMOS
1.8
–
1.64
1.5 V LVCMOS (JESD8-11)
1.5
–
0.99
3.3 V PCI
3.3
–
17.64
3.3 V PCI-X
3.3
–
17.64
Notes:
1. PDC6 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VMV.
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Revision 3