M1A3P1000-1PQ208M Datasheet, PDF (31/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero IDE software.
The power calculation methodology described below uses the following variables:
• The number of PLLs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 on
page 2-19.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-23 on
page 2-19.
• Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-23 on page 2-19. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P_TOTAL
P_TOTAL = P_STAT + P_DYN
P_STAT is the total static power consumption.
P_DYN is the total dynamic power consumption.
Total Static Power Consumption—P_STAT
P_STAT = (PDC0 or PDC1 or PDC2 or PDC3) + N_BANKS* P_DC5 + N_INPUTS* PDC6 + N_OUTPUTS* PDC7
N_INPUTS is the number of I/O input buffers used in the design.
N_OUTPUTS is the number of I/O output buffers used in the design.
N_BANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—P_DYN
P_DYN = P_CLOCK + P_S-CELL + P_C-CELL + P_NET + P_INPUTS + P_OUTPUTS + P_MEMORY + P_PLL
Global Clock Contribution—P_CLOCK
P_CLOCK = (PAC1 + N_SPINE * PAC2 + N_ROW * PAC3 + N_S-CELL* PAC4) * F_CLK
N_SPINE is the number of global spines used in the user design—guidelines are provided in
Table 2-22 on page 2-19.
N_ROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-22 on page 2-19.
F_CLK is the global clock signal frequency.
N_S-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P_S-CELL
P_S-CELL = N_S-CELL * (PAC5 + ₁ / 2 * PAC6) * F_CLK
N_S-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
₁ is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on
page 2-19.
F_CLK is the global clock signal frequency.
Revision 3
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