M1A3P1000-1PQ208M Datasheet, PDF (135/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Global Resource Characteristics
Military ProASIC3/EL Low Power Flash FPGAs
A3P1000 Clock Tree Topology
Clock delays are device-specific. Figure 2-42 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-42 is driven by a CCC located on the west side of the A3P1000 device.
It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-42 • Example of Global Tree Use in an A3P1000 Device for Clock Routing
Revision 3
2- 121