M1A3P1000-1PQ208M Datasheet, PDF (124/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
CLK
Data_F
1
Data_R 6
t_DDROSUD2 t_DDROHD2
2
3
4
t_DDROREMCLR ^tDDROHD1
7
8
9
CLR
t_DDROREMCLR
t_DDROCLR2Q
Out
t_DDROCLKQ
7
2
8
3
5
10
t_DDRORECCLR
9
4
11
10
Figure 2-37 • Output DDR Timing Diagram
Timing Characteristics
Table 2-185 • Output DDR Propagation Delays
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
t_DDROCLKQ
Clock-to-Out of DDR for Output DDR
0.97 1.14 ns
t_DDRISUD1
Data_F Data Setup for Output DDR
0.52 0.62 ns
t_DDROSUD2
Data_R Data Setup for Output DDR
0.52 0.62 ns
t_DDROHD1
Data_F Data Hold for Output DDR
0.00 0.00 ns
t_DDROHD2
Data_R Data Hold for Output DDR
0.00 0.00 ns
t_DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.11 1.30 ns
t_DDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00 0.00 ns
t_DDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.31 0.36 ns
t_DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19 0.22 ns
t_DDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR
0.31 0.36 ns
t_DDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR
0.28 0.32 ns
F_DDOMAX
Maximum Frequency for the Output DDR
TBD TBD MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
2-110
Revision 3