M1A3P1000-1PQ208M Datasheet, PDF (39/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military
Conditions—Software Default Settings
Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only
I/O Standard
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
Strength Option¹ Rate V
VIL
Max.
V
VIH
VOL
VOH
I_OL2 I_OH2
Min.
V
Max.
V
Max.
V
Min.
V
mA mA
3.3 V LVTTL / 12 mA 12 mA High –0.3
0.8
3.3 V LVCMOS
2
3.6
0.4
2.4
12 12
3.3 V LVCMOS 100 µA 12 mA High –0.3
0.8
Wide Range^1,3
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS 12 mA 12 mA High –0.3
0.7
1.7
2.7
0.7
1.7
12 12
1.8 V LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45 VCCI – 0.45 12 12
1.5 V LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. Currents are measured at 125°C junction temperature.
3. Output slew rate can be extracted using the IBIS Models.
4. Output drive strength is below JEDEC specification.
5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military
Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only
I/O Standard
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
Strength Option¹ Rate V
VIL
Max.
V
VIH
VOL
Min.
V
Max.
V
Max.
V
VOH
I_OL2 I_OH2
Min.
V
mA mA
3.3 V LVTTL / 12 mA 12 mA High –0.3
0.8
3.3 V LVCMOS
2
3.6
0.4
2.4
12 12
3.3 V LVCMOS 100 µA 12 mA High –0.3
0.8
Wide Range^1,3
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS 12 mA 12 mA High –0.3
0.7
1.7
2.7
0.7
1.7
12 12
1.8 V LVCMOS 8 mA 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45 VCCI – 0.45 8 8
1.5 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. Currents are measured at 125°C junction temperature.
3. Output slew rate can be extracted using the IBIS Models.
4. Output drive strength is below JEDEC specification.
5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Revision 3
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