M1A3P1000-1PQ208M Datasheet, PDF (33/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1
= 50%
– Bit 2
= 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-22 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
₁
Toggle rate of VersaTile outputs
₂
I/O buffer toggle rate
Guideline
10%
10%
Table 2-23 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
₁
I/O output buffer enable rate
₂
RAM enable rate for read operations
₃
RAM enable rate for write operations
Guideline
100%
12.5%
12.5%
Revision 3
2- 19