M1A3P1000-1PQ208M Datasheet, PDF (46/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Table 2-35 • I/O Output Buffer Maximum Resistances ¹
Applicable to Pro I/Os for A3PE600L and A3PE3000L Only
Standard
3.3 V LVTTL / 3.3 V LVCMOS
Drive Strength
4 mA
R_PULL-DOWN () ²
100
R_PULL-UP () ³
300
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range
100 µA
Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
4 mA
100
200
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
1.2 V LVCMOS⁴
1.2 V LVCMOS Wide Range⁴
12 mA
2 mA
100 µA
33
37
158
158
158
158
3.3 V PCI/PCI-X
3.3 V GTL
2.5 V GTL
Per PCI/PCI-X specification
25
75
20 mA⁵
11
–
20 mA⁵
14
–
3.3 V GTL+
35 mA
12
–
2.5 V GTL+
33 mA
15
–
HSTL (I)
HSTL (II)
8 mA
15 mA⁵
50
50
25
25
SSTL2 (I)
15 mA
27
31
SSTL2 (II)
18 mA
13
15
SSTL3 (I)
14 mA
44
69
SSTL3 (II)
21 mA
18
32
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.actel.com/download/ibis/default.aspx.
2. R_{(PULL-DOWN-MAX)} = (VOLspec) / I_OLspec.
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / I_OHspec.
4. Applicable to A3PE600L and A3PE3000L devices operating in the 1.2 V core range only.
5. Output drive strength is below JEDEC specification.
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Revision 3