M1A3P1000-1PQ208M Datasheet, PDF (20/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
VCC
VCC = 1.575 V
VCC = 1.14 V
Activation trip point:
V_a = 0.85 V ± 0.2 V
Deactivation trip point:
V_d = 0.75 V ± 0.2 V
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Region 1: I/O Buffers are OFF
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 1: I/O buffers are OFF
Activation trip point:
V_a = 0.9 V ± 0.15 V
Deactivation trip point:
V_d = 0.8 V ± 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
VCCI
Figure 2-3 • Device Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage
Levels; Only A3PE600L and A3PE3000L Devices Operate at 1.2 V Core Voltage
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Revision 3