M1A3P1000-1PQ208M Datasheet, PDF (166/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Pin Descriptions and Packaging
VCOMPLA/B/C/D/E/F PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and-
route tool automatically disables the unused PLLs to lower power consumption. The user should tie
unused VCCPLx and VCOMPLx pins to ground.
• There is one VCOMPLF pin on A3P250 and A3P1000 devices.
• There are six VCOMPL pins (PLL ground) on A3PE600L and A3PE3000L devices.
VJTAG
JTAG Supply Voltage
Military ProASIC3/EL devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be
run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
A3P250 and A3P1000 devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User-Defined Supply Pins
VREF
I/O Voltage Reference
Reference voltage for I/O minibanks in A3PE600L and A3PE3000L devices. VREF pins are configured
by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated the voltage
reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and
(II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its
minibank.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
• Output buffer is disabled (with tristate value of high impedance)
• Input buffer is disabled (with tristate value of high impedance)
• Weak pull-up is programmed
3-2
Revision 3