M1A3P1000-1PQ208M Datasheet, PDF (147/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Table 2-204 • RAM4K9
Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000
Parameter
Description
–1 Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
0.30 0.35 ns
0.00 0.00 ns
0.17 0.20 ns
0.12 0.14 ns
0.28 0.33 ns
0.02 0.03 ns
0.22 0.26 ns
0.00 0.00 ns
2.84 2.53 ns
2.15 3.33 ns
t_CKQ2
t_C2CWWL
Clock High to new data valid on DO (pipelined)
1.08 1.27 ns
Address collision clk-to-clk delay for reliable write after write on same address – 0.28 0.33 ns
applicable to closing edge
t_C2CWWH Address collision clk-to-clk delay for reliable write after write on same address – 0.26 0.30 ns
applicable to rising edge
t_C2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.38 0.45 ns
address – applicable to opening edge
t_C2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.42 0.49 ns
address – applicable to opening edge
t_RSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
1.11 1.31 ns
1.11 1.31 ns
t_REMRSTB RESET_B removal
0.34 0.40 ns
t_RECRSTB RESET_B recovery
1.81 2.12 ns
t_MPWRSTB RESET_B minimum pulse width
0.26 0.30 ns
t_CYC
Clock cycle time
3.89 4.57 ns
F_MAX
Maximum frequency
257 219 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.
Revision 3
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