M1A3P1000-1PQ208M Datasheet, PDF (2/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
I/Os Per Package ¹
ProASIC3/EL
Low Power Devices
A3P250
A3PE600L
A3P1000
A3PE3000L
ARM
Cortex-M1 Devices
M1A3P1000
M1A3PE3000L
Package
Single- Differential Single- Differential Single- Differential Single- Differential
Ended I/O² I/O Pairs Ended I/O² I/O Pairs Ended I/O² I/O Pairs Ended I/O² I/O Pairs
VQ100
68
13
–
–
–
–
–
–
PQ208
–
–
–
–
154
35
–
–
FG144
–
–
–
–
97
25
–
–
FG484
–
–
270
135
300
74
341
168
FG896
–
–
–
–
–
–
620
300
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to
ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page III for the location of the
"G" in the part number.
4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
Military ProASIC3/EL Device Status
Military ProASIC3/EL Devices
A3P250
A3PE600L
A3P1000
A3PE3000L
Status
Production
Production
Production
Production
M1 Military ProASIC3/EL Devices
M1A3P1000
M1A3PE3000L
Status
Production
Production
II
Revision 3