M1A3P1000-1PQ208M Datasheet, PDF (155/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Table 2-209 • FIFO
Worst Military-Case Conditions: T_J = 125°C, VCC = 1.425 V for A3PE600L and
A3PE3000L
Parameter
Description
–1 Std. Units
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
t_CKQ2
t_RCKEF
t_WCKFF
t_CKAF
t_RSTFG
t_RSTAF
t_RSTBQ
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
WCLK HIGH to Full Flag Valid
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
1.46 1.71 ns
0.02 0.02 ns
0.40 0.47 ns
0.00 0.00 ns
0.19 0.23 ns
0.00 0.00 ns
2.50 2.93 ns
0.95 1.11 ns
1.82 2.14 ns
1.73 2.03 ns
6.56 7.71 ns
1.79 2.11 ns
6.49 7.63 ns
0.98 1.15 ns
0.98 1.15 ns
t_REMRSTB
RESET_B Removal
0.30 0.36 ns
t_RECRSTB
RESET_B Recovery
1.59 1.87 ns
t_MPWRSTB RESET_B Minimum Pulse Width
0.59 0.67 ns
t_CYC
Clock Cycle Time
5.39 6.20 ns
F_MAX
Maximum Frequency for FIFO
185 161 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating
values.
Revision 3
2- 141