M1A3P1000-1PQ208M Datasheet, PDF (138/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Table 2-198 • A3P250 Global Resource
Military-Case Conditions: T_J = 125°C, VCC = 1.425 V
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
Input Low Delay for Global Clock
0.97 1.24 1.14 1.46 ns
t_RCKH
Input High Delay for Global Clock
0.94 1.27 1.11 1.49 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
ns
t_RCKSW
Maximum Skew for Global Clock
0.32
0.38 ns
F_RMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating
values.
Table 2-199 • A3P1000 Global Resource
Military-Case Conditions: T_J = 125°C, VCC = 1.425 V
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
Input Low Delay for Global Clock
1.18 1.44 1.39 1.70 ns
t_RCKH
Input High Delay for Global Clock
1.17 1.48 1.37 1.74 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
ns
t_RCKSW
Maximum Skew for Global Clock
0.32
0.37 ns
F_RMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating
values.
2-124
Revision 3