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M1A3P1000-1PQ208M Datasheet, PDF (115/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
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Military ProASIC3/EL Low Power Flash FPGAs
Timing Characteristics
Table 2-174 • Output Data Register Propagation Delays
Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
0.81 0.96 ns
tOSUD
Data Setup Time for the Output Data Register
0.43 0.51 ns
tOHD
Data Hold Time for the Output Data Register
0.00 0.00 ns
tOSUE
Enable Setup Time for the Output Data Register
0.61 0.71 ns
tOHE
Enable Hold Time for the Output Data Register
0.00 0.00 ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.11 1.31 ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.11 1.31 ns
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00 ns
tORECCLR Asynchronous Clear Recovery Time for the Output Data Register
0.31 0.36 ns
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00 ns
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register
0.31 0.36 ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19 0.22 ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19 0.22 ns
tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register
0.31 0.36 ns
tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register
0.28 0.32 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
Table 2-175 • Output Data Register Propagation Delays
Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L
Parameter
Description
–1 Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
0.62 0.73 ns
tOSUD
Data Setup Time for the Output Data Register
0.33 0.39 ns
tOHD
Data Hold Time for the Output Data Register
0.00 0.00 ns
tOSUE
Enable Setup Time for the Output Data Register
0.46 0.55 ns
tOHE
Enable Hold Time for the Output Data Register
0.00 0.00 ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
0.85 1.00 ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
0.85 1.00 ns
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00 ns
tORECCLR Asynchronous Clear Recovery Time for the Output Data Register
0.24 0.28 ns
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00 ns
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register
0.24 0.28 ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19 0.22 ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19 0.22 ns
tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register
0.31 0.36 ns
tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register
0.28 0.32 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
Revision 3
2- 101
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