M1A3P1000-1PQ208M Datasheet, PDF (139/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Clock Conditioning Circuits
Military ProASIC3/EL Low Power Flash FPGAs
CCC Electrical Specifications
Timing Characteristics
Table 2-200 • Military ProASIC3/EL CCC/PLL Specification
For Devices Operating at 1.2 V DC Core Voltage: Applicable to A3PE600L and A3PE3000L Only
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency
f_{IN_CCC}
Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}
Delay Increments in Programmable Delay Blocks ^{1, 2}
1.5
250
MHz
0.75
250
360
MHz
ps
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL³
32
100
MHz
Input cycle-to-cycle jitter (peak magnitude)
1
ns
Acquisition Time
LockControl = 0
300
µs
Tracking Jitter⁴
LockControl = 1
6.0
ms
LockControl = 0
25
ns
LockControl = 1
1.5
ns
Output Duty Cycle
Delay Range in Block: Programmable Delay 1 ^1,2
Delay Range in Block: Programmable Delay 2 ^1,2
Delay Range in Block: Fixed Delay ^1,2
CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}
48.5
51.5
%
1.2
15.65
ns
0.025
15.65
ns
3.5
ns
Max. Peak-to-Peak Period Jitter^5,6
SSO  2 SSO  4 SSO  8 SSO  16
0.75 MHz to 50 MHz
0.50% 0.60% 0.80% 1.60%
50 MHz to 160 MHz
2.50% 4.00% 6.00% 12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings.
2. T_J = 25°C, VCC = 1.2 V.
3. Maximum value obtained for a –1 speed grade device in worst-case military conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
5. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14V, VQ/PQ/TQ
type of packages, 20 pF load.
6. Switching I/Os are placed outside of the PLL bank.
Revision 3
2- 125