M1A3P1000-1PQ208M Datasheet, PDF (146/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
Table 2-203 • RAM4K9
Military-Case Conditions: T_J = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L
Parameter
Description
–1
Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
0.26 0.31 ns
0.00 0.00 ns
0.15 0.18 ns
0.10 0.12 ns
0.25 0.29 ns
0.02 0.02 ns
0.19 0.23 ns
0.00 0.00 ns
2.50 2.93 ns
1.89 2.22 ns
t_CKQ2
t_C2CWWL
Clock HIGH to new data valid on DO (pipelined)
0.95 1.11 ns
Address collision clk-to-clk delay for reliable write after write on same address – 0.24 0.29 ns
applicable to closing edge
t_C2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.20 0.24 ns
address – applicable to opening edge
t_C2CRWH
Address collision clk-to-clk delay for reliable write access after read on same 0.25 0.30 ns
address – applicable to opening edge
t_RSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
0.98 1.15 ns
0.98 1.15 ns
t_REMRSTB RESET_B removal
0.30 0.36 ns
t_RECRSTB RESET_B recovery
1.59 1.87 ns
t_MPWRSTB RESET_B minimum pulse width
0.59 0.67 ns
t_CYC
Clock cycle time
5.39 6.20 ns
F_MAX
Maximum frequency
185 161 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
2-132
Revision 3