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| M1A3P1000-1PQ208M Datasheet, PDF (113/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology | |||
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Military ProASIC3/EL Low Power Flash FPGAs
Table 2-173 ⢠Input Data Register Propagation Delays
Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000
Parameter
Description
â1 Std. Units
tICLKQ
Clock-to-Q of the Input Data Register
0.29 0.34 ns
tISUD
Data Setup Time for the Input Data Register
0.32 0.37 ns
tIHD
Data Hold Time for the Input Data Register
0.00 0.00 ns
tISUE
Enable Setup Time for the Input Data Register
0.45 0.53 ns
tIHE
Enable Hold Time for the Input Data Register
0.00 0.00 ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.55 0.64 ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.55 0.64 ns
tIREMCLR Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00 ns
tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register
0.27 0.31 ns
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00 ns
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register
0.27 0.31 ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.25 0.30 ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.25 0.30 ns
tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register
0.41 0.48 ns
tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register
0.37 0.43 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.
Revision 3
2- 99
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