M1A3P1000-1PQ208M Datasheet, PDF (45/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL Low Power Flash FPGAs
Table 2-33 •
Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.425 V,
Worst Case VCCI
Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5 – 0.54 1.90 0.04 0.94 0.39 1.94 1.47 2.61 3.01 4.03 3.56
3.3 V LVCMOS 100 µA
Wide Range³
12 mA High 5 – 0.54 2.94 0.04 1.42 0.39 2.94 2.22 4.03 4.66 6.12 5.40
2.5 V LVCMOS
12 mA 12 mA High 5 – 0.54 1.94 0.04 1.21 0.39 1.97 1.62 2.64 2.91 4.07 3.71
1.8 V LVCMOS
8 mA
8 mA High 5 – 0.54 1.94 0.04 1.21 0.39 1.97 1.62 2.64 2.91 4.07 3.71
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
4 mA
Per PCI
spec.
Per PCI-X
spec.
4 mA High 5 – 0.54 2.62 0.04 1.33 0.39 2.67 2.23 2.84 2.93 4.77 4.32
– High 10 25 ⁴ 0.54 2.16 0.04 0.80 0.39 2.20 1.60 2.61 3.01 4.29 3.69
– High 10 25 ⁴ 0.54 2.16 0.04 0.78 0.39 2.20 1.60 2.61 3.01 4.29 3.69
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a
specific output load, refer to Designer software. Software default load is higher.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for
connectivity. This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.
Detailed I/O DC Characteristics
Table 2-34 • Input Capacitance
Symbol
Definition
C_IN
C_INCLK
Input capacitance
Input capacitance on the clock pin
Conditions
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
Min.
Max.
8
8
Units
pF
pF
Revision 3
2- 31