M1A3P1000-1PQ208M Datasheet, PDF (120/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Military ProASIC3/EL DC and Switching Characteristics
DDR Module Specifications
Input DDR Module
Input DDR
Data
INBUF
A
D
Out_QF
(to core)
FF1
B
CLK
CLKBUF
E
Out_QR
(to core)
FF2
CLR
C
INBUF
DDR_IN
Figure 2-34 • Input DDR Timing Model
Table 2-180 • Parameter Definitions
Parameter Name
Parameter Definition
t_DDRICLKQ1
t_DDRICLKQ2
t_DDRISUD
t_DDRIHD
t_DDRICLR2Q1
t_DDRICLR2Q2
t_DDRIREMCLR
t_DDRIRECCLR
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
Measuring Nodes (from, to)
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
2-106
Revision 3